1. Technical Field of the Invention
The present invention relates in general to integrated circuits, especially memory cells. More particularly, the present invention relates to memory cells of the dynamic random access memory (DRAM) type and more particularly to on-board memories of the embedded dynamic random access memory (eDRAM) type that are compatible with a process for fabricating a device incorporating such a memory and CMOS components.
2. Description of Related Art
Conventionally, a DRAM memory takes the form of a matrix of rows and columns at the intersections of which there are memory cells consisting of a memory element, typically a capacitor, and a switch for controlling this memory element, in general an MOS transistor.
A DRAM memory cell typically comprises an MOS control transistor and a storage capacitor that are connected in series between a reference and a bit line. The gate of the control transistor is connected to a word line. The transistor controls the flow of electric charge between the capacitor and the bit line. The electric charge on the capacitor determines the logic level, 1 or 0, of the memory cell. Upon read-out of the memory cell, the capacitor is discharged into the bit line.
A large number of DRAM cells thus constructed are assembled in the form of a matrix so as to generate a memory plane that may comprise millions of elementary cells. The memory plane is, for some applications, located within a complex integrated circuit. The memory is then said to be on-board (or embedded) memory.
There is a need for an integrated circuit having a higher memory cell density.
There is a need to reduce the size of the components of a DRAM memory.
There is also a need to reduce the effects of size reduction on the performance of such a memory.